The present invention generally relates to semiconductor devices, and more particularly to a semiconductor package that includes a semiconductor chip formed with solder bumps for mounting the chip on a package substrate with a flip-chip process.
With the increase in the integration density of semiconductor integrated circuits, the number of electrode pads on a semiconductor chip is increasing, and such an increase in the electrode pads inevitably results in a corresponding decrease in the mutual distance therebetween. In such very large scale integrated circuits, therefore, the conventional package structure of the SIP type or DIP type is not suitable, as the tip ends of inner leads tend to contact with each other because of the reduced mutual separation between the electrode pads. A similar problem occurs also in multiple chip modules wherein a number of integrated circuit chips are mounted on a common package substrate.
In order to achieve a successful electric connection to such high performance integrated circuits, a flip-chip process is proposed wherein the electrode pads are formed on the entirety of the lower major surface of the semiconductor chip in a row and column formation and wherein the semiconductor chip is placed on the upper major surface of a package substrate such that the electrode pads establish an electric connection with corresponding electrodes provided on the upper major surface of the package substrate. The electric connection between the electrode pad and corresponding electrode is achieved by providing a solder bump in correspondence to each of the electrode pads and causing a reflow of the solder by passing the semiconductor chip through a heating furnace together with the package substrate. According to the flip-chip process, one can increase the number of electrode pads formed on the semiconductor chip significantly, without causing a contact with each other.
However, when the number of the electrode pads is excessive, there still occurs the problem of unwanted contact of adjacent electrode pads even when the flip-chip process is used. In the flip-chip process, the chance that adjacent solder bumps may contact each other as a result of the reflowing of the solder increases with the increasing number of electrode pads and hence with decreasing distance between the solder bumps. Thus, there is a need for an improvement of the flip-chip process in order to apply the flip-chip process to semiconductor devices where a large number of electrode pads are formed on the chip surface with a reduced separation.
Meanwhile, the semiconductor chips are generally subjected to a so-called "burn-in" process before the device is shipped to the user in order to ensure the proper operation of the device. In the burn-in process, a predetermined voltage is applied to predetermined electrode pads on the chip to simulate a severe operational condition that the chip may encounter during the use of the device. After the burn-in process, those chips that showed a failure are discarded. In such a burn-in process, it is necessary to provide an electrical contact to the minute electrode pads. Such an electrical contact is difficult to achieve in the devices where the separation between the electrode pads is very small. Generally, such an electrical contact is achieved by a sharp-pointed probe needle. The contact by the probe needle tends to cause a damage to the solder bump that is provided on the electrode pad. Once the solder bump is damaged, there is a substantial risk that the electrical connection between the chip and the package substrate will become defective.
FIG. 1 shows a conventional semiconductor chip 1 designed for the flip-chip process. There, the chip 1 includes a chip body 2 defined by a bottom surface 2a, and a number of electrode pads are formed substantially on the entirety of the surface 2a in a row and column formation. Thereby, a very large number of electrode pads can be formed on a single chip body 2. It should be noted that each electrode pad is provided with a corresponding solder bump 3 for external electrical connection.
FIG. 2 shows the structure of a semiconductor package 4 that accommodates therein the chip 1 of FIG. 1. There, the semiconductor package 4 includes a package substrate 7 of a ceramic material, and the package substrate 7 carries an interconnection pattern 10 on the upper major surface thereof. The semiconductor chip 1 is mounted on the upper major surface of the substrate 7 by a flip-chip process such that each solder bump 3 on the surface 2a establishes a contact with the interconnection pattern 10. Then, the substrate 7 and the chip 1 are passed through a furnace to cause a reflowing of the solder bump 3 as shown in FIG. 3.
In FIG. 3, it will be noted that the distance between the lower major surface 2a of the chip 2 and the upper major surface 10a of the interconnection pattern 10, designated in FIG. 3 as "T," is an essential factor for proper electrical connection between the electrode pad on the chip 1 and the interconnection pattern 10. When the distance T is excessively large, the contact between the solder bump and the interconnection pattern may not occur. On the other hand, when the distance T is excessively small, the molten solder bump 3 may spread laterally and cause an unwanted short circuit.
Referring to FIG. 2 again, the substrate 7 has a lower major surface 7a wherein a number of electrode pads are formed in electrical connection with the interconnection pattern 10, and the electrode pads at the surface 7a are covered by corresponding solder bumps 11. Further, the semiconductor chip 1 is covered by a cap or enclosure 6 that is bonded to the substrate 7 by solder 8 such that the cap 6 forms a closed space together with the substrate 7 for accommodating therein the semiconductor chip 1. It should be noted that the chip 1 is bonded to the cap 6 at the upper major surface of the chip body 2 by solder 5. Thereby, the chip 1 is hermetically sealed within the package 4.
In such a conventional package structure, the solder bumps 3 may contact with each other upon reflowing when the distance T of FIG. 3 is insufficient. Thus, although the structure of FIG. 2 may be advantageous for increasing the number of electrode pads, there exists a limitation in the number of the electrode pads that can be formed on the surface 2a of the chip 1. In the devices where there are a large number of solder bumps separated from each other by a minute distance, the proper setting of the distance T becomes an essential factor for increasing the yield of the device.
FIGS. 4(A) and 4(B) show the conventional process of burn-in as applied to the semiconductor chip 1 of FIG. 1.
Referring to FIGS. 4(A) and 4(B), the semiconductor chip 1 is mounted on a jig 13 that has one or more probe needles 12 in correspondence to the solder bumps 3 that cover the electrode pads to which a burn-in voltage is to be applied.
As shown in FIG. 4(A), the jig 13 has a stepped side wall part 13a for holding a side wall 2b of the chip 1 firmly. Alternatively, the chip 1 may be fixed against the jig 13 by a solder bump 3a that fits into a depression 13b formed on the side wall part of the jig 13 for fixing the chip 1 to the jig 13 upon reflowing as shown in FIG. 4(B).
In any of these conventional burn-in processes, the probe needles 12 are urged resiliently against the solder bumps 3 by the action of a spring, and a predetermined voltage is applied for causing the burn-in. Thereby, the sharp-pointed end of the probe needle 12 may penetrate into the solder bump 3 and cause damage thereto. When such a semiconductor chip having damage in the solder bump 3 is used in the flip-chip process to form the package structure of FIG. 2, the wetting of the solder upon reflowing may be degraded and the risk of defective electric connection increases. Further, the burn-in process as shown in FIGS.4(A) and 4(B) cannot be applied to the devices wherein a very large number of electrode pads are formed on the surface of the chip body with a minute mutual separation because of the mechanical limitation in the reduction of mutual separation between the probe needles.